1. Field
The embodiments discussed herein relate to a storage apparatus.
2. Description of Related Art
Data may be written in a memory cell in a semiconductor storage apparatus, such as a ferroelectric random access memory (FeRAM) or dynamic random access memory (DRAM) by an activating word line in accordance with a row address. In a DRAM, a word line is activated and a voltage is applied to one end of a memory capacitor via a cell transistor. When writing data in an FeRAM, a word line is activated, data of a bit line is written in a memory cell via a cell transistor and the word line is deactivated after writing the data. In a FeRAM, both a word line and a plate line are activated to write data in a ferroelectric cell.
Related technologies are disclosed in Japanese Laid-open Patent Publication No. H11-353879, Japanese Laid-open Patent Publication No. H11-308855, and non-patent Japanese-language document, Kiyoo Ito, “Advanced Electronics Series I-9: VLSI Memory” pp. 310-315, 1994 November, Bifukan.